In FIG. 1, there is shown one of conventional phase-locked loop frequency synthesizers which is described in Japanese patent application laid-open No. 136037/1981 published on Oct. 23, 1981. The phase-locked loop frequency synthesizer comprises an oscillator 1 for producing a reference frequency, a fixed divider 2 for dividing the reference frequency by the fixed ratio thereof, a phase detector 3 for detecting the difference of frequencies and phases between the divided frequency and an output frequency of a programmable divider 7 to be described later, a low pass filter 5 connected to phase detector 3 through an analog switch 10 to be controlled by a control signal 12 to be applied to a control signal terminal CT, a voltage-controlled oscillator (VCO)6 for producing an output frequency proportional to the phase difference in the phase detector 3, the above mentioned programmable counter 7 for dividing the frequency produced in the VCO 6 by a dividing factor of a programmed integer, and a power source switch 11 to be controlled by the control signal 12 to connect the respective circuits to a power source PS.
In operation, when the control signal 12 is high ("1"), the analog switch 10 and the power source switch 11 are turned on at time t.sub.1 in FIG. 2 so that the phase-locked loop frequency synthesizer is operated. That is to say, the phase detector 3 compares the frequency and phase of the output from the VCO 6 with those of the reference divider 2 to produce a mean DC voltage proportional to the frequency and phase differences in accordance with the comparison thereof. The mean DC voltage is fed back to a frequency varying means in the VCO 6 which decreases the frequency and phase differences by changing the frequency of the output therefrom to result in a phase-locked loop operation as illustrated by "LOCK" in FIG. 2.
On the other hand, when the control signal 12 is low ("0"), the analog switch 10 and the power source switch 11 are turned off at time t.sub.2 in FIG. 2 so that the phase-locked loop frequency synthesizer is in an open loop as illustrated by "OPEN" in FIG. 2.
In the construction of a phase-locked loop frequency synthesizer mentioned above, there is provided a capacitance of a relatively large capacity at the output of the low pass filter 5 and a varactor diode to be biased reversely to result in an extremely high impedance at the input of the VCO 6.
Even in the operation of the open loop, therefore, the low pass filter 5 preserves a predetermined level of a voltage which is charged in a phase-locked loop and applies the voltage to the frequency varying means of the VCO 6. In such a condition, the voltage applied to the input of the VCO 6 is maintained to be constant for a short time. Substantially, however, the voltage is gradually decreased due to the self discharge of the capacitance of the low pass filter 5 and the leakage current flowing through the resistance of the turned-off analog switch 10 so that the output frequency of the VCO 6 is gradually decreased as illustrated by "D" in FIG. 2. In a predetermined time interval, the analog switch 10 and the power source switch 11 are turned on and off respectively at times t.sub.3, t.sub.4, t.sub.5, and t.sub.6 in FIG. 2 in accordance with the high and low of the control signal 12 in a manner mentioned above.
As clearly understood from the above descriptions, less consumption of electric power is achieved in a phase-locked loop frequency synthesizer by alternately repeating the operations of closed loop and open loop while the stability of frequency is obtained therein in a predetermined range.
According to a phase-locked loop frequency synthesizer mentioned above, however, when the analog switch 10 and the power source switch 11 are turned on to provide the phase-locked loop operation, the output frequency of the VCO 6 is fluctuated in accordance with the initial phase difference Q.sub.1, Q.sub.2 or Q.sub.3 (Q.sub.2 &gt;Q.sub.1 &gt;Q.sub.3) of the outputs between the fixed divider 2 and the programmable divider 7 as shown in FIG. 2. Therefore, longer time is necessary to result in a phase lock due to the larger frequency fluctuation if the initial phase difference is larger therein. In such a case, the larger a dividing factor M of the programmable divider 7 is, the greater the influence of the initial phase difference between the outputs of the fixed and programmable dividers is because the output frequency of the VCO 6 is varied in accordance with the phase difference to be multiplied by the dividing factor M. Therefore, the disadvantage due to the initial phase difference as described herein is inevitable even if a VCO having a higher open loop frequency stabilization is adopted therein.